1. Field of the Invention
The present invention relates to computer graphics systems, and more specifically to a method and apparatus for generating a clock signal synchronized with a reference clock signal.
2. Related Art
There is often a need to generate a clock signal ("target clock signal") which is synchronized with a reference clock signal. The two clock signals generally have unequal frequencies. For the purpose of illustration, the target clock signal may need to have a frequency of X/Y times the frequency of the reference clock signal, wherein X and Y are integers.
U.S. Pat. No. 5,739,867 entitled, "A Method and Apparatus for Upscaling an Image in Both Vertical and Horizontal Directions", Issued Apr. 14, 1998, naming as inventor Alexander Julian Eglit, discloses an example situation in which such a need arises. The patent discloses a scaling circuit which scales a source image of A.times.B pixels into a destination image of C.times.D pixels without requiring large memories. The scaling circuit there scales the image by using a destination clock signal having ((C.times.D)/(A.times.B)) times the frequency of a source clock. The source clock is used as a reference clock and the destination clock is the target clock signal.
In a prior system, synchronization may be achieved by dividing a target clock signal by X and the source system clock by Y, comparing the phase of the resulting divided clock signals, and adjusting the phase of the target clock signal. Such a technique may be used in environments using digital or analog phase lock loops (PLLs) as is well known in the relevant arts.
In general, a target clock signal is more accurately synchronized with a reference clock signal if the time between successive comparisons ("comparison cycles") is small because the shorter comparison cycles enable the phase of the target clock signal to be adjusted more frequently. Accordingly, both X and Y may be divided by a common denominator (CD), and the resulting numbers may be respectively used instead of X and Y. The comparison cycles may be shorter proportionate to the CD. in the upscaler embodiment noted above, the number of comparison cycles within a frame equals the CD used to divide (A.times.B ) and (C.times.D).
However, it may not be possible to make the comparison cycles short in several situations. For example, in the above technique, the greatest common denominator (GCD) of X and Y can be a number as low as 1. Such a situation may be further illustrated with the upscaler of U.S. Pat. No. 5,739,867. If a source image of size 800.times.600 pixels is to be upscaled to an image of size 1901.times.1501, only a very low GCD may be present. The upscaled image size may be specified by a user using a suitable user interface. A low GCD may lead to large comparison cycles.
Large comparison cycles may be problematic in several situations. For example, in techniques using PLLs to generate a target clock signal, large synchronization periods may result in large settling times and phase jitter. Phase jitter typically leads to display artifacts. Large settling times may be unacceptable as the tracking and correction abilities of the PLLs may be under-utilized. The problems caused by underutilization depend on the environment in which the PLL is used. For example, a monitor (e.g., using an upscaler according to U.S. Pat. No. 5,739,867) may take unacceptably long time in starting to display an image when a target image size is changed.
Furthermore, computation of CDs for large numbers and/or the division of X and Y by the CD may require unacceptably long time or complex circuits.
Accordingly, what is needed is an effective method and apparatus for synchronizing a target clock signal with a reference clock signal.